Logic Analyser 1.0

Introduction

System Requirements

Logic Analyser requires a TI-82 calculator running OS-82. The program takes up 933 bytes of memory. No additional memory is allocated while running. Some kind of interface circuit is also recommended.

Distribution Contents

The distribution of Logic Analyser should contain the following files:

logic	82p	The TI-82 program file
logic	asm	The source code in Z80 assembly language
diodes	gif	Schematic for a simple diode interface circuit
mosfet	gif	Schematic for a MOSFET interface circuit
sample	gif	Sample screenshot of Logic Analyser displaying data from Mac Plus keyboard
logic	htm	This file
intrface	txt	Text file describing interface circuits
logic	txt	Plain text documentation
source	txt	Source code documentation
os82	zip	Distribution of TI-82 assembly shell

Using Logic Analyser

First download the file "logic.82p" to your calculator. Then run OS-82 and select Logic Analyser from the software menu. You will then see the Logic Analyser screen with the program title at the top, a status line, two lines displaying the setting and two lines with the names of the channels and their connections on the link port.

Now plug your interface circuit into the calculator's link port (or SPiNTERFACE port if fitted) and connect the probes to the circuit under test. If you attach the interface circuit to the calculator before you run Logic Analyser, your calculator may appear to hang. This is normal, simply unplug the interface and the calculator should return to normal operation. You should also disconnect the interface circuit before exiting from Logic Analyser.

Select a trigger mode and sampling delay with the arrow keys. The up and down arrows switch between changing trigger mode and the sampling delay. The left and right arrow keys change the trigger mode or the sampling delay. Press the CLEAR key to exit from Logic Analyser.

The sample modes are as follows:

Manual:	Triggers immediately.
Channel 1 Rising:	Triggers when the Channel 1 signal undergoes a low to high transition.
Channel 1 Falling:	Triggers when the Channel 1 signal undergoes a high to low transition.
Channel 2 Rising:	Triggers when the Channel 2 signal undergoes a low to high transition.
Channel 2 Falling:	Triggers when the Channel 2 signal undergoes a high to low transition.

The sampling delay setting corresponds to the number of DJNZ instructions (rather like a FOR loop) executed between samples. The higher this number the lower the sample rate. Values range from 000 to 255. At 000, you can neatly capture a byte from an AT keyboard. At 255, a byte on a 300bps serial bus takes up most of the screen.

When you press ENTER, Logic Analyser goes into the "armed" state and waits for a trigger event to occur. When the trigger event occurs, Logic Analyser takes 96 samples and graphs them on the screen. Note that, to minimise response time, Logic Analyser does not read the keypad while it is waiting for a trigger event, so the program must be triggered before you can exit. This can be ach by momentarily shorting both channel inputs to ground.

Note that Logic Analyser, to avoid hanging when connected to a live circuit, does not support APD, sleep between keystrokes, the Get( instruction from another calculator or the TI-GraphLink Get LCD from TI-82 command.

Interface Circuits

The most basic interface circuit would simply be two power diodes, e.g. 1N4004, connected cathode to circuit, anode to link port to prevent the input from being pulled above 5V. However, this wouldn't keep the input from being pulled below 0V. To solve this problem, and to protect against faulty diodes (don't laugh, I had a 1N4007 that would have made a convincing 7V zener!), I recommend adding two zener diodes connected anode to ground and cathodes to the link port inputs as shown below. This circuit will allow the calculator to be connected to 5V TTL circuits and 5-18V CMOS.

For supply voltages lower than 5V, you'll need a slightly more complex cicuit. The one shown below will work with TTL and CMOS with supply voltages down to 3V. Note that this circuit acts as an inverter.

Another approch would be to use a level shifter IC such as the 40109. The input supply pin would be connected to the circuit under test's supply rail and the output supply pin would be connected to a +5V rail. This could be taken from your calculator's SPiNTERFACE port if you've fitted one.

Source Code Information

The source code to Logic Analyser is provided so you can see how an assembly language program works on a TI-82 calculator. It contains examples of simple user interaction, reading from the link port and display manipulation. Also, if you are observing very low speed circuitry, you may want to re-compile Logic Analyser with some NOPs in the delay loop, or you could take the delay out altogether for higher speed.

Please do not distribute any modified copies of Logic Analyser or its source code! I can't provide support for software I haven't written.

I do realise that the code would be easier to understand if it was more structured, but on the TI-82 you only have 28.5 kB of RAM, and you do all you can to make your program as small as possible.

You may use code from Logic Analyser in non-commercial programs as long as at least 50% of the program is your own work. Also, if more than three lines of code are copied, you must acknowledge me in the program credits. Also, if the source code of the program is distributed, any three consecutive lines copied from Logic Analyser must be acompanied by a comment "Courtesy Vasantha Crabb".

Credits

Without Jimmy Mardels's ASH School, this program would have taken ten times as long to write. Also, the port, RAM and ROM documentation provided with ASH has been invaluable.

Disclaimer and Copyright

Logic Analyser is provided "as is". Although I have taken measures to ensure its reliability and safety, I cannot guarantee that no problems remain. I accept no responsibility for any damage which Logic Analyser may cause, directly or indirectly, to your calculator, your data or the circuits you use ot to test.

Logic Analyser is Copyright © 1999 Vasantha Crabb. You may distribute unmodified copies of the zip archive between computers, or unmodified copies of the program between calculators. You may use the source code in your own projects, as long as it constitutes no more than fifty percent of the total code and I am acknowledged in the credits. You may not distribute modified copies of the program, the documentation or the source code without my express permission. You may not use source code from logic analyser in any commercial software.

Future Plans

• Add waveform storage features, once I figure out how to work the VAT.
• Determine the actual sampling speed, although this depends on the CPU clock speed, which may not be right on 6 MHz.

Version History

1.0 15 April 1999

Initial release. Two channels, five triggering modes, wide range of sample rates.